From: Heiko Stuebner <heiko@sntech.de>
Date: Mon, 5 Aug 2019 14:44:36 +0000 (+0200)
Subject: rockchip: rk3399: store actual debug uart information on suspend
X-Git-Url: http://git.openwrt.org/%22https:/collectd.org//%22http:/www.crowdsec.net/%22/%22https:/collectd.org/%22http:/www.crowdsec.net/%22?a=commitdiff_plain;h=0eb7fa91e18bd888d94cd8d92f033ba92d9cb818;p=project%2Fbcm63xx%2Fatf.git

rockchip: rk3399: store actual debug uart information on suspend

The rk3399 suspend code saves and restores the debug uart settings, but
right now always does this for the default uart. Right now this works
only by chance for the majority of rk3399 boards, which do not deviate
from that default.

But both Coreboot as well as U-Boot-based platforms can actually use
different uarts for their output, which can be configured from either
devicetree or Coreboot-variables.

To fix this, just use the stored uart-base information instead of the
default constant.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: I1ea059d59a1126f6f8702315df7e620e632b686e
---

diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index a6b59736..30941fd0 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1125,32 +1125,41 @@ static struct uart_debug uart_save;
 
 void suspend_uart(void)
 {
-	uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
-	uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
-	uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
+	uint32_t uart_base = rockchip_get_uart_base();
+
+	if (uart_base == 0)
+		return;
+
+	uart_save.uart_lcr = mmio_read_32(uart_base + UART_LCR);
+	uart_save.uart_ier = mmio_read_32(uart_base + UART_IER);
+	uart_save.uart_mcr = mmio_read_32(uart_base + UART_MCR);
+	mmio_write_32(uart_base + UART_LCR,
 		      uart_save.uart_lcr | UARTLCR_DLAB);
-	uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
-	uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
+	uart_save.uart_dll = mmio_read_32(uart_base + UART_DLL);
+	uart_save.uart_dlh = mmio_read_32(uart_base + UART_DLH);
+	mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
 }
 
 void resume_uart(void)
 {
+	uint32_t uart_base = rockchip_get_uart_base();
 	uint32_t uart_lcr;
 
-	mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
+	if (uart_base == 0)
+		return;
+
+	mmio_write_32(uart_base + UARTSRR,
 		      XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
 
-	uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
-	mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
+	uart_lcr = mmio_read_32(uart_base + UART_LCR);
+	mmio_write_32(uart_base + UART_MCR, DIAGNOSTIC_MODE);
+	mmio_write_32(uart_base + UART_LCR, uart_lcr | UARTLCR_DLAB);
+	mmio_write_32(uart_base + UART_DLL, uart_save.uart_dll);
+	mmio_write_32(uart_base + UART_DLH, uart_save.uart_dlh);
+	mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
+	mmio_write_32(uart_base + UART_IER, uart_save.uart_ier);
+	mmio_write_32(uart_base + UART_FCR, UARTFCR_FIFOEN);
+	mmio_write_32(uart_base + UART_MCR, uart_save.uart_mcr);
 }
 
 void save_usbphy(void)